1. Field of the Invention
The present invention relates to a semiconductor test apparatus for testing an analog circuit (e.g., an analog-to-digital converter or a digital-to-analog converter) which is one of LSIs to be tested (hereinafter called xe2x80x9cDUTsxe2x80x9d) by an LSI test apparatus (hereinafter called xe2x80x9ctesterxe2x80x9d), as well as to a method of testing a semiconductor device using the semiconductor test apparatus.
2. Background Art
Recently, in relation to a system LSI (embodied in a one-chip LSI consisting of a plurality of functionally-systematized circuit modules or embodied in a chip set LSI), combination of digital and analog circuits (i.e., a system LSI handling a mixed signal), having high-performance and precision, has been rapidly pursued. In order to cope with such a tendency, tester manufacturers have provided testers compatible with a semiconductor integrated circuit using a mixed signal. A tester compatible with a semiconductor integrated circuit using a mixed signal has high performance specifications and inevitably becomes expensive. For this reason, one proposed resolution is recycling an existing low-speed, low-precision tester (e.g., a tester for a logic LSI), to thereby avoid a hike in the price of a tester.
A big problem with such a test apparatus lies in a characteristic test for a converter circuit for converting a digital signal into an analog signal (digital-to-analog converter, hereinafter called a xe2x80x9cDACxe2x80x9d) as well as in a characteristic test for a converter circuit for converting an analog signal into a digital signal (hereinafter called an xe2x80x9cADCxe2x80x9d). In a testing environment of a general tester, connection jigs for connecting a tester with a DUT, such as a plurality of DUT circuit boards (simply called xe2x80x9cDUT boardsxe2x80x9d) and cables, are provided at a plurality of points along a measurement path extending from measurement equipment provided in the tester to a DUT. Further, the measurement path is long and accounts for occurrence of noise and a drop in measurement accuracy. A limitation is imposed on the speed of a low-speed tester, and hence the low-speed tester cannot conduct a test at a real operating speed, thereby posing a fear of an increase in a time required for conducting mass-production testing of a system LSI.
FIG. 7 is a block diagram showing a BOST device of a related-art semiconductor test apparatus which has been conceived for shortening a test time according to a method of testing a DAC of a DUT and which employs a technique for conducting a test through use of an external ADC disposed in the vicinity of a DUT.
As shown in the drawing, reference numeral 1 designates a tester; 2 designates a DUT; 3 designates a digital-to-analog converter section of the DUT 2; 4 designates an output section of the DUT 2; 5 designates a CPU of the DUT 2; 6 designates an analog-to-digital converter section; 7 designates a digital signal entered by way of the tester 1; 8 designates an analog signal produced through digital-to-analog conversion; 9 designates a digital signal produced through analog-to-digital conversion; 10 designates a CPU of the tester 1; 11 designates RAM; 12 designates a signal for controlling input/output operations of the RAM 11; and 13 designates a digital signal output from the RAM 11.
The operation of the BOST device will now be described.
The digital signal 7 entered by way of the tester 1 is converted into an analog signal by means of the digital-to-analog converter section 3 of the DUT 2. The thus-converted signal is further subjected to analog-to-digital conversion in the analog-to-digital converter 6, and the thus-converted data are stored in the RAM 11. After all these operations have been performed, the data stored in the RAM 11 are output. The thus-output data and the data input to the digital-to-analog converter section 3 of the DUT 2 are compared by the tester 1, thus making an evaluation of the DAC.
FIG. 8 is a block diagram showing a BOST device of a related-art semiconductor test apparatus which has been conceived for shortening a test time according to a method of testing an ADC of a DUT and which employs a technique for conducting a test through use of an external DAC disposed in the vicinity of a DUT. In FIG. 8, elements which are identical with those shown in FIG. 7 are assigned the same reference numerals, and repeated explanations thereof are omitted.
As shown in FIG. 8, reference numeral 14 designates a digital-to-analog converter; 15 designates a DUT; 16 designates an analog-to-digital converter section of the DUT 15; 17 designates an output section of the DUT 15; and 18 designates a CPU of the DUT 15.
The operation of the BOST device will now be described.
The digital signal 7 entered by way of the tester 1 is subjected to digital-to-analog conversion in the digital-to-analog converter 14, and the thus-converted signal is further subjected to analog-to-digital conversion in the analog-to-digital conversion section 16 of the DUT 15. Further the thus-converted data are stored in the RAM 11. After all these operations have been performed, the data stored in the RAM 11 are output. The thus-output data and the data input to the digital-to-analog converter 14 are compared by the tester 1, thus making an evaluation of the ADC.
The related-art semiconductor test apparatus shown in FIG. 7 suffers the following problems.
All data, addresses, and control signals stored in measured data storage memory; i.e., RAM, connected to an external ADC; i.e., an analog-to-digital converter, must be supplied from a tester [a CPU and a timing pattern generator (TPG)]. The majority of pin electronics provided on a tester are occupied for testing a single ADC, thus imposing limitations on simultaneous measurement of a plurality of ADCs. Test results are evaluated after all tests have been completed. Hence, an effect of shortening a time required for effecting a real test is small. Further, measured data must be uploaded to a CPU of the tester, thus resulting in a chance of an increase arising in a processing time including communications time. Further, the related-art semiconductor test apparatus has failed to describe a control method and procedures and is devoid of specificity of a method of shortening a test time.
The related-art semiconductor test apparatus shown in FIG. 8 suffers the same problem as that encountered by the related-art test apparatus shown in FIG. 7.
The present invention has been conceived to solve the problems set forth and is aimed at providing a semiconductor test apparatus which is susceptible of simultaneously measuring a plurality of DUTs, enables shortening of a real test time, and obviates a necessity for uploading measured data to a CPU of the tester, as well as providing a method of testing a semiconductor device using the semiconductor test apparatus.
According to one aspect of the present invention, a semiconductor test apparatus comprises an analog-to-digital converter for converting into a digital signal an analog output from a circuit under test. Further the apparatus comprises a test-apparatus-ADC-control-signal generation circuit for generating a control signal for the analog-to-digital converter in accordance with an activation signal from the outside or the inside. Further the apparatus comprises a measured data memory for storing, as measured data for each conversion, a signal output from the analog-to-digital converter. Further the apparatus comprises an address counter for generating an address signal for the measured data memory. Further the apparatus comprises a DAC counter for generating data to be input to the circuit under test. Further the apparatus comprises a data write control circuit which produces, in response to a flag signal output from the analog-to-digital converter and representing that conversion is being performed, an update signal for the address counter, a memory write signal for the measured data memory, and an update signal for the DAC counter.
According to another aspect of the present invention, a semiconductor test apparatus comprises digital-to-analog converter for producing an analog input to a circuit under test. Further the apparatus comprises a measured data memory for storing, as measured data for each conversion, a signal which has been output from the circuit under test and has been subjected to analog-to-digital conversion. Further the apparatus comprises an address counter for generating an address signal for the measured data memory. Further the apparatus comprises a DAC counter for generating data to be input to the digital-to-analog converter. Further the apparatus comprises a data write control circuit for producing, in response to a flag signal which is output from the circuit under test and represents that conversion is being performed, an update signal for the address counter, a memory write signal for the measured data memory, and an update signal for the DAC counter.
According to another aspect of the present invention, a semiconductor test apparatus comprises an analog-to-digital converter for converting into a digital signal an analog output from a circuit under test. Further the apparatus comprises a digital-to-analog converter for producing an analog input to be sent to the circuit under test. Further the apparatus comprises a measured data memory for storing, as measured data for each conversion, a signal output from the analog-to-digital converter and a signal which has been output from the circuit under test and has been subjected to analog-to-digital conversion. Further the apparatus comprises an address counter for generating an address signal for the measured data memory. Further the apparatus comprises a DAC counter for producing data to be input to the circuit under test and to the digital-to-analog converter. Further the apparatus comprises a data write control circuit for producing, in response to a flag signal which has been output from the analog-to-digital converter and from the circuit under test and which represents that conversion is being performed, an update signal for the address counter, a memory write signal for the measured data memory, and an update signal for the DAC counter. Further the apparatus comprises a digital signal processor analysis section for reading measured data from the measured data memory and computing a characteristic parameter pertaining to the circuit under test, thus evaluating predetermined specifications.
Other and further objects, features and advantages of the invention will appear more fully from the following description.